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[AK7742]
= Preliminary =
AK7742
24bit 2ch ADC + 24bit 4ch DAC with Audio DSP
GENERAL DESCRIPTION The AK7742 is a highly integrated audio digital processor, including two stereo 24bit DAC's and one stereo ADC with input selector. The stereo DAC and ADC feature high performance, archiving 106dB and 96dB dynamic range respectively, 8kHz to 96kHz sampling rate are supported. The audio DSP has 1536step/fs parallel processing power, and 74k-bit delay memory allows surround processing, acoustic effect and parametric equalizers. As the AK7742 is a RAM based DSP, it is programmable for user requirements. The AK7742 is available in a space saving small 48pin LQFP package. FEATURES
DSP:
- Word length: 24bit (Data RAM 24bit floating point) - Instruction cycle: 13.6 ns (1536step/fs fs=48kHz; 9216step/fs fs=8kHz) - Multiplier 20 x 16 36bit (double precision available) - Divider 20 / 20 20bit - ALU: 40bit arithmetic operation (overflow margin 4bit) 24bit floating point arithmetic and logic operation - Program RAM: 1536 x 36bit - Coefficient RAM: 1536 x 16bit - Data RAM: 1536 x 24-bit (24bit floating point) - Delay RAM: 74kbit (3072 x 24bit) - Sampling frequency: 8kHz ~ 96kHz - Master / Slave operation - Serial signal input port (4ch) MSB justified 24bit / LSB justified 24 / 20 / 16bit and I2S - Serial signal output port (6ch) MSB justified 24bit / LSB justified 24 / 16bit and I2S ADC: 2ch (stereo) - 24bit 64 x Over-sampling delta sigma (fs=8kHz~48kHz) - DR, S/N: 96dB (fs=48kHz, fully differential input) - S/(N+D): 84dB (fs=48kHz) - Differential, Single-end Inputs - Digital HPF (fc=1Hz) - 3:1 Analog input selector - Digital Volume (24dB~-103dB, 0.5dB Step, Mute) DAC: 4ch (two stereo pairs) - 24bit 128 x Over-sampling advanced multi-bit (fs=8kHz~96kHz) - DR, S/N: 106dB - S/(N+D): 92dB - Differential output - Digital Volume (24dB~-103dB, 0.5dB Step, Mute) DSP Through Mode
I2C BUS interface for micro-controller Power supply: +3.3V 0.3V, internal regulator for 1.8V Operating temperature range: -20C~70C Package: 48pin LQFP (0.5mm pitch)
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[AK7742]
Block Diagram
LFLT XTO pull down Hi-z Open Drain XTI BICK LRCK IRESETN CKM[2:0] TESTI
2 DVDD 3 VSS1 3 3 AVDD 2 VSS2
CLKGEN & CONT
3
SELDO3
REF
ASEL[1:0]
VCOM AVDRV
CLKO/SDOUT3
CLKOE
DVOL
ADC
2 1
2 2
AIN3L,AIN3R AIN2L,AIN2R
0 1
SDOUTAD
0
4
AIN1LP,AIN1LN AIN1RP,AIN1RN
DIN3
DOUT3
SELDO5[1:0] DOUT5
0 1 2 3
DVOL
DAC2
AOUT2LP AOUT2LN AOUT2RP AOUT2RN
SDINDA2
JX0E SDIN2 / JX0
JX0 DIN2 DOUT4
0 1 2 3
DVOL
DAC1
AOUT1LP AOUT1LN AOUT1RP AOUT1RN
SDINDA1
JX1E SDIN1 / JX1
JX1 DIN1 DOUT1
SELDO4[1:0]
1 0
OUT1E
SDOUT1
SELDO1 DOUT2 GPO
SELDO2[1:0]
3 2
OUT2EN
SO/RDY/GPO/SDOUT2
MICIF DS
RDY SO
1 0
I2CSEL CAD1 SCL CAD0 SDA
Figure 1. Block Diagram
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[AK7742]
CP0, CP1
DP0, DP1
DLP0, DLP1 DLRAM 3072W x 24-Bit OFREG 64W x 13-Bit
CRAM 1536W x 16-Bit
DRAM 1536W x 24-Bit
CBUS(16-Bit) DBUS(24-Bit)
MPX16
MPX20
Micon I/F Control PRAM 1536w x 36-Bit PC Stack : 5level(max) 24-Bit TMP 8 x 24-Bit PTMP(LIFO) 6 x 24-Bit Serial I/F
X Multiply 16 x 20 36-Bit
Y
DEC
36-Bit MUL 40-Bit
DBUS SHIFT 40-Bit
A ALU 40-Bit
B
2 x 24,16-Bit
DIN3 (ADC)
2 x 24,20,16-Bit DIN2 2 x 24,20,16-Bit DIN1 2 x 24,16-Bit 40-Bit 2 x 24,16-Bit 2 x 24,20,16-Bit 2 x 24,20,16-Bit 2 x 24,20,16-Bit DOUT5 (DAC2) DOUT4 (DAC1) DOUT3 DOUT2 DOUT1
Overflow Margin: 4-Bit 40-Bit DR0 3
Over Flow Data Generator
Division
20/2020
Peak Detector
Figure 2. AK7742 DSP Block
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[AK7742]
Ordering Guide
AK7742EQ AKD7742 -20 +70C 48pin LQFP (0.5mm pitch) Evaluation board for the AK7742
Pin Layout
SO/RDY/GPO/SDOUT2 25
AOUT2RP
AOUT2LP
AOUT2LN
AOUT2RN
AVDD
AVDRV
CAD0
CAD1
VSS1
36
35
34
33
32
31
30
29
28
27
SCL
AOUT1RN AOUT1RP AOUT1LN AOUT1LP VSS1 VCOM AVDD AIN1RN AIN1RP AIN1LN AIN1LP AIN3R
37 38 39 40 41 42 43 44 45 46 47 48
26
SDA
24 23 22 21 20 19 18 17 16 15 14 13 10 11 12 1 2 3 4 5 6 7 8 9
CLKO/SDOUT3 BICK LRCK VSS2 DVDD I2CSEL IRESET CKM[0] CKM[1] SDIN2/JX0 SDIN1/JX1 SDOUT1
48pin LQFP
(TOP VIEW)
XTI
CKM[2]
VSS1
AIN3L
AIN2R
AVDD
TESI1
AIN2L
DVDD
VSS2
XTO
LFLT
pin
Input Output I/O Power
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[AK7742]
PIN FUNCTION
No. 1 2 3 4 5 I/O Function Classification I ADC Lch Single-end input 3 pin Analog input I ADC Rch Single-end input 2 pin Analog input I ADC Lch Single-end input 2 pin Analog input Power supply pin for analog section 3.0V ~ 3.6V Analog power supply Analog ground 0V Analog power supply Filter connection pin for PLL 6 LFLT O Analog output Connect C=12nF to VSS1. "L" output during initial reset. Test pin (internal pull-down resistor) 7 TESTI I Test Connect to VSS2 8 CKM[2] I Clock mode select pin 2 Mode select 9 DVDD Power supply pin for digital section 3.0V ~ 3.6V Digital power supply 10 VSS2 Digital ground 0V Digital power supply Master clock input pin 11 XTI I When using a crystal oscillator, connect it between this pin and XTO. Clock When using external main clock, input to this pin with CMOS level. Crystal oscillator output pin When using a crystal oscillator, connect it between this pin and XTI. 12 XTO O Clock When not using crystal oscillator, leave open. Output during initial reset is not determined. O DSP serial data output pin 13 SDOUT1 Data interface "L" output during initial reset 14 SDIN1/JX1 I Serial data input pin 1 / JX1 Data interface 15 SDIN2/JX0 I Serial data input pin 2 / JX0 Data interface 16 CKM[1] I Clock mode select pin 1 Mode select 17 CKM[0] I Clock mode select pin 0 Mode select 18 IRESETN I Reset pin (for initialization) Reset I2CBUS select pin 19 I2CSEL I Microcomputer I/F Connect to DVDD 20 DVDD Power supply pin for digital section 3.0V ~ 3.6V Digital power supply 21 VSS2 Digital ground 0V Digital power supply I/O LR channel select clock pin 22 LRCK Data interface "L" output during initial reset with master mode. I/O Serial bit clock pin 23 BICK Data interface "L" output during initial reset with master mode. O Clock output / DSP serial data output pin 24 CLKO/SDOUT3 Clock "L" output during initial reset Serial data output pin / Data write ready output pin / General purpose output SO/RDY/GPO/ 25 O / DSP serial data output pin Microcomputer I/F SDOUT2 "L" output during initial reset 26 SDA I/O SDA I2C bus interface Microcomputer I/F 27 SCL I SCL I2C bus interface Microcomputer I/F 28 CAD0 I I2C bus address pin 0 Microcomputer I/F 29 CAD1 I I2C bus address pin 1 Microcomputer I/F 30 VSS1 Analog ground 0V Analog power supply Pin name AIN3L AIN2R AIN2L AVDD VSS1
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[AK7742]
31 AVDRV 32 AVDD 33 AOUT2RN 34 AOUT2RP 35 AOUT2LN 36 AOUT2LP 37 AOUT1RN 38 AOUT1RP 39 AOUT1LN 40 AOUT1LP 41 VSS1 42 VCOM 43 44 45 46 47 48 AVDD AIN1RN AIN1RP AIN1LN AIN1LP AIN3R
O
O O O O O O O O
O
I I I I I
AVDRV Pin Connect 1F to VSS1. Never to use for external circuit. "L" output during Analog power supply initial reset Power supply pin for analog section 3.0V ~ 3.6V Analog power supply DAC2 Rch differential inverted analog output pin Analog output "Hi-Z" output during initial reset DAC2 Rch differential non-inverted analog output pin Analog output "Hi-Z" output during initial reset DAC2 Lch differential inverted analog output pin Analog output "Hi-Z" output during initial reset DAC2 Lch differential non-inverted analog output pin Analog output "Hi-Z" output during initial reset DAC1 Rch differential inverted analog output pin Analog output "Hi-Z" output during initial reset DAC1 Rch differential non-inverted analog output pin Analog output "Hi-Z" output during initial reset DAC1 Lch differential inverted analog output pin Analog output "Hi-Z" output during initial reset DAC1 Lch differential non-inverted analog output pin Analog output "Hi-Z" output during initial reset Analog ground 0V Analog power supply Analog common voltage Connect 0.1F and 2.2F in parallel to VSS1. Never to use for external Analog output circuit. "L" output during initial reset Power supply pin for analog section 3.0V ~ 3.6V Analog power supply ADC Rch differential inverted analog input pin Analog input ADC Rch differential non-inverted analog input pin Analog input ADC Lch differential inverted analog input pin Analog input ADC Lch differential non-inverted analog input pin Analog input ADC Rch Single-end input 3 pin Analog input
Note: Digital input pins are never to be left open. If analog input pins (AIN1LP, AIN1LN, AIN1RP, AIN1RN, AIN2L, AIN2R, AIN3L, AIN3R) are not used, leave them open.
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[AK7742]
ABSOLUTE MAXMUM RATING (VSS1=VSS2=0V: Note 1) Item Symbol min max Power supply voltage (AVDD= DVDD) Analog AVDD -0.3 4.3 Digital DVDD -0.3 4.3 Input current (except for power supply pin) IIN 10 Analog input voltage (Note 2) AIN1LP, AINL1N, AIN1RP, AINR1N, VINA -0.3 (AVDD+0.3) or 4.3 AIN2L, AIN2R, AIN3L, AIN3R Digital input voltage (Note 3) VIND -0.3 (DVDD+0.3) or 4.3 Operating ambient temperature Ta -20 70 Storage temperature Tstg -65 150 Note 1. All indicated voltages are with respect to ground. VSS1 and VSS2 must be the same voltage. Note 2. The maximum value of analog input voltage is smaller value between (AVDD+0.3)V and 4.3V. Note 3. The maximum value of digital input voltage is smaller value between (DVDD+ 0.3)V and 4.3V.
Unit V V mA V V C C
WARNING: Operating at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these critical conditions.
RECOMMENDED OPERATING CONDITIONS
(VSS1=VSS2=0V: Note 1) Item Power supply voltage Analog Digital Symbol AVDD DVDD min 3.0 3.0 typ 3.3 3.3 max 3.6 3.6 Unit V V
WARNING: AKEMD assumes no responsibility for the usage beyond the conditions in the datasheet. Note) Do not turn off the power of the AK7742 during the power supplies of surrounding devices are turned on. VDD must not exceed the pull-up of SDA and SCL of I2C BUS. (The diode exists for DVDD in the SDA and SCL pins.)
Rev.0.5b_PB
-7-
2008/08
[AK7742]
ANALOG CHARACTERISTICS
ADC Characteristics
(Ta=25C; AVDD=DVDD=3.3V; BICK=64fs; signal frequency 1kHz; Measurement bandwidth=20Hz~20kHz, fs=48kHz, ADC differential input, CKM mode 0 (CKM[2:0]=000), unless otherwise specified) Parameter min typ max Unit Resolution 24 Bits Stereo ADC Dynamic characteristics S/(N+D) (-1dBFS) (Note 4) TDB 84 dB Dynamic range (A-weighted) (Note 4) TDB 96 dB S/N (A-weighted) (Note 4) TDB 96 dB Inter-channel isolation (f=1kHz) (Note 5) 90 105 dB DC accuracy Channel gain mismatch 0.1 0.3 dB Analog input Input voltage (differential input) (Note 6) 1.85 2.00 2.15 Vp-p Input voltage (single-end input) (Note 7) 1.85 2.00 2.15 Vp-p 41 62 k Input impedance (Note 8) Note 4. This value is not guaranteed for single-ended inputs. Note 5. Indicates isolation between L and R when -1dBFS signal is applied. Note 6. Target input pins are AIN1LP, AIN1LN, AIN1RP, AIN1RN. Note 7. Target input pins are AIN2L, AIN2R, AIN3L, AIN3R. Note 8. Target input pins are AIN1LP, AIN1LN, AIN1RP, AIN1RN, AIN2L, AIN2R, AIN3L, AIN3R.
DAC Characteristics
(Ta=25C; AVDD=DVDD=3.3V; BICK=64fs; signal frequency 1kHz; Measurement bandwidth=20Hz~20kHz, fs=48kHz, ADC differential input, CKM mode 0 (CKM[2:0]=000), unless otherwise specified) Parameter min typ max Unit Resolution 24 Bits Stereo DAC Dynamic characteristics S/(N+D) (0dBFS) TBD 92 dB Dynamic range (A-weighted) TBD 106 dB S/N (A-weighted) TBD 106 dB Inter-channel isolation (f=1kHz)(Note 9) 90 105 dB DC accuracy Channel gain mismatch 0.2 0.5 dB Analog output Output voltage (Note 10) 3.36 3.66 3.96 Vp-p Load resistance 5 k Load capacitance 30 pF Note 9. Indicates isolation between each DAC's of Lch and Rch when -1dBFS signal is applied. Note 10. Full scale output voltage. The output voltage scales with AVDD.
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[AK7742]
DC CHARACTERISTICS (Ta=-20C ~70C; AVDD=DVDD=3.0~3.6V) Parameter Symbol min High level input voltage (Note 11) VIH 80%DVDD Low level input voltage (Note 11) VIL SCL, SDA High level input voltage VIH 70%DVDD SCL, SDA Low level input voltage VIL VOH DVDD-0.5 High level output voltage Iout=-100A VOL Low level output voltage Iout=100A (Note 12) SDA Low level output voltage Iout=3mA VOL Input leak current (Note 13) Iin Input leak current (pull-down) (Note 14) Iid Input leak current XTI pin Iix
Note 11. Except for the SCL, SDA pin. Note 12. Except for the SDA pin. Note 13. Except for the TESTI pin, XTI pin. Note 14. The TESTI pin has an internal pull-down device, nominally 150k.
typ
max 20%DVDD 30%DVDD 0.5 0.4 10
22 26
Unit V V V V V V V A A A
POWER CONSUMPTION (Ta=25C; AVDD=DVDD=3.0~3.6V(typ=3.3V, max=3.6V)) Parameter min typ max Unit Power supply current (Note 15) Normal Operation 75 TBD mA AVDD+DVDD Reset (IRESETN= "L" reference data) 2 mA AVDD+DVDD (Note 16) Note 15. Depends on the system frequency and contents of DSP program. Note 16. This is a reference value when using a crystal oscillator. Since most of the supply current at the initial reset state is in the oscillator section, the value may vary according to the crystal type and the external circuit. This value is just reference.
Rev.0.5b_PB
-9-
2008/08
[AK7742]
DIGITAL FILTER CHARACTERISTICS
ADC
(Ta=-20C ~70C, AVDD=DVDD=3.0~3.6V, fs=48kHz; Note 17) Parameter Symbol min typ max Unit Pass band (0.005dB) (Note 18) PB 0 21.5 kHz (-0.02dB) 21.768 kHz (-6.0dB) 24.00 kHz Stop band SB 26.5 kHz Pass band ripple (Note 18) PR 0.005 dB Stop band attenuation (Note 19, Note 20) SA 80 dB Group delay distortion GD 0 s Group delay (Ts=1/fs) GD 30 Ts Digital filter + Analog filter characteristics Amplitude characteristic 20Hz~20.0kHz 0.01 dB Note 17. Each parameter is related to the sampling frequency (fs). HPF response is not included. Note 18. Pass band is from DC to 21.5kHz when fs=48kHz. Note 19. Stop band is from 26.5kHz to 3.0455MHz when fs=48kHz. Note 20. When fs=48kHz, the analog modulator samples the analog input at 3.072MHz. Therefore the input signal is not attenuated by the digital filter in multiple bands (n x 3.072MHz 21.99kHz; n=0, 1, 2, 3 ...) of the sampling frequency.
DAC
(Ta=-20C ~70C, AVDD=DVDD=3.0~3.6V, fs=48kHz; Note 17) Parameter Symbol min typ max Unit Digital filter Pass band 0.07dB (Note 21) PB 0 21.7 kHz (-6.0dB) 24.0 kHz Stop band (Note 21) SB 26.2 kHz Pass band ripple PR 0.01 dB Stop band attenuation SA 64 dB Group delay (Ts=1/fs) (Note 22) GD 24 Ts Digital filter + Analog filter Amplitude characteristic 0~20.0kHz 0.5 dB Note 21. Pass band and Stop band parameter is related to sampling frequency(fs). PB=0.4535fs (at-0.05dB), SB=0.5465fs. Note 22.The digital filter's delay is calculated as the time from setting 24-bit data into the input register until an analog signal is output.
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[AK7742]
SWITCHING CHARACTERISTICS
System Clock
(Ta=-20C~70C; AVDD=DVDD=3.0~3.6V) Parameter Symbol XTI a)with a crystal oscillator Frequency(256fs) fs=44.1KHz fXTI fs=48KHz CKM[2:0]= 000 CKM[2:0]= 001 fXTI b)with an external clock Duty cycle
Frequency(256fs) CKM[2:0]= 000, 010 Frequency (384fs) CKM[2:0]= 001 fs=44.1KHz fs=48KHz fs=44.1KHz fs=48KHz
min
typ
max
Unit
-
11.2896 12.288 16.9344 18.432 50 11.2896 12.288
16.9344 18.432
-
MHz MHz
Duty fXTI
fXTI
40 11.0
16.5
60 12.4
18.6
% MHz
MHz
LRCK frequency (Note 23)
Fs
7.35
48
96
kHz
BICK frequency 32 64 fs a) CKM[2:0]= 001, 010 High level width tBCLKH 64 ns Low level width tBCLKL 64 ns Frequency 0.46 3.072 6.144 MHz fBCLK 64 fs b) CKM[2:0]= 011 (Note 25) Duty cycle Duty 40 50 60 % Frequency fBCLK 2.75 3.072 3.1 MHz 32 fs c) CKM[2:0]= 100 (Note 26) Duty cycle Duty 40 50 60 % Frequency fBCLK 230 256 258 kHz 64 fs d) CKM[2:0]= 101 (Note 27) Duty cycle Duty 40 50 60 % Frequency fBCLK 460 512 516 kHz Note 23. LRCK frequency and sampling rate (fs) should be the same. Note 24. The BICK must be divided 32, 48 or 64 clocks correctly. (BICK can be selected from 32fs, 48fs or 64fs) Note 25. When BICK is resource of internal MCLK. The BICK must be divided 64 clocks correctly. 64fs fixed. Note 26. When BICK is resource of internal MCLK. The BICK must be divided 32 clocks correctly. 32fs fixed. Note 27. When BICK is resource of internal MCLK. The BICK must be divided 64 clocks correctly. 64fs fixed.
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[AK7742]
Reset
(Ta=-20C ~70C; AVDD=DVDD=3.0~3.6V) Parameter Symbol min typ max Unit IRESET (Note 28) tRST 600 ns Note 28. It is necessity that the power is supplied and master clock is input when the IRESET pin goes to "H".
Audio Interface
1) SDIN1, SDIN2, SDOUT1, SDOUT2, SDOUT3
(Ta=-20C ~70C; AVDD=DVDD=3.0~3.6V, CL=20pF) Parameter Slave mode BICK frequency BICK low level width BICK high level width Delay time from BICK "" to LRCK (Note 29) Delay time from LRCK to BICK "" (Note 29) Serial data input latch setup time Serial data input latch hold time Delay time from LRCK to serial data output Delay time from BICK "" to serial data output (Note 30) Master mode BICK frequency BICK duty cycle Delay time from BICK "" to LRCK Delay time from LRCK to BICK "" Serial data input latch setup time Serial data input latch hold time Delay time from BICK "" to serial data output (Note 30)
Symbol fBCLK tBCLKL tBCLKH tBLRD tLRBD tBSIDS tBSIDH tLRD tBSOD fBCLK tBLRD tLRBD tBSIDS tBSIDH tBSOD
min 32 150 150 40 40 40 40 -10 -10
typ 64
max
Unit fs ns ns ns ns ns ns ns ns fs % ns ns ns ns ns
40 40 64 50
40 40 40 40 -30
40
Note 29. BICK rising edge must not occur at the same time as LRCK edge. Note 30. The serial data output is synchronized to BICK falling edge, and held until next BICK falling (spec -10ns) in Slave mode. In case of the LRCK edge comes before BICK edge, data will be held until LRCK edge (spec -10ns). In Master mode, serial data is held until 30ns before falling edge of BICK. Therefore, please use BICK rising edge in both slave and master modes for a safety latch. .
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[AK7742]
I2CBUS Interface
(Ta=-20C~70C; AVDD=DVDD=3.0~3.6V) Parameter I2C Timing SCL clock frequency Bus Free Time Between Transmissions Start Condition Hold Time (prior to first Clock pulse) Clock Low Time Clock High Time Setup Time for Repeated Start Condition SDA Hold Time from SCL Falling SDA Setup Time from SCL Rising Rise Time of Both SDA and SCL Lines Fall Time of Both SDA and SCL Lines Setup Time for Stop Condition Pulse Width of Spike Noise Suppressed by Input Filter Capacitive load on bus Symbol fSCL tBUF tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR tF tSU:STO tSP Cb min typ max 400 1.3 0.6 1.3 0.6 0.6 0 0.1 Unit KHz s s s s s s s s s s ns pF
0.9 0.3 0.3
0.6 0
50 400
Note 31. I2C is a registered trademark of Philips Semiconductors.
Rev.0.5b_PB
- 13 -
2008/08
[AK7742]
PACKAGE
48pin LQFP (Unit: mm)
9.0 0.2 7.0 36 37 25 24 9.0 0.2
1.70Max 0.13 0.13 1.4 0.05
48 1 0.5 0.22 0.08 12
13
7.0
0.09 0.20 0.10 M
0 10
0.10
0.3 0.75
Materials and Lead Specification
Package: Lead frame: Lead-finish: Epoxy Copper Soldering (Pb free) plate
Rev.0.5b_PB
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2008/08
[AK7742]
MARKING
AK7742EQ
XXXXXXX
1
1) 2) 3) 4) Pin #1 indication Date Code: XXXXXXX(7digits) Marking Code: AK7742EQ Asahi Kasei Logo
AKM
IMPORTANT NOTICE These products and their specifications are subject to change without notice. When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei EMD Corporation (AKEMD) or authorized distributors as to current status of the products. AKEMD assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of any information contained herein. Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. AKEMD products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or other hazard related device or systemNote2), and AKEMD assumes no responsibility for such use, except for the use approved with the express written consent by Representative Director of AKEMD. As used here: Note1) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. It is the responsibility of the buyer or distributor of AKEMD products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKEMD harmless from any and all claims arising from the use of said product in the absence of such notification.
Rev.0.5b_PB
- 15 -
2008/08
[AK7742]
Thank you for your access to AKEMD product information. More detail product information is available, please contact our sales office or authorized distributors.
Rev.0.5b_PB
- 16 -
2008/08

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